1. Field of the Invention
The present invention relates to a multilevel metallization structure and a method for manufacturing the same adapted for a semiconductor integrated circuit device.
2. Related Art
Recently, integrated circuit devices constituting a semiconductor memory, a microcomputer, etc. have been remarkably increased in integration density of the elements thereof, thereby enabling the semiconductor memory and the microcomputer to improve their electric performance.
A fine patterning technology plays an important role in the process of integration and recently requires an IC design in accordance with a 0.5 .mu.m design rule. Most of the large-scale integrated circuit devices adopt a multilevel metallization structure having fine metallizations.
Whereupon, if the metallization becomes more fine, there is a likelihood of generating metallization breakage because of the occurrence of stress migration or electromigration so that the metallizations have a multilevel metallization structure composed of different conductive material levels to thereby maintain a reliability. For example, a level formed of TiN, TiW or WSi is laid under an Al metallization as an migration resistant level.
In a double-level metallization structure, since the Al metallization has a high reflectance, the accuracy of a metallization patterning made by a photolithographic technology is deteriorated, which leads to the occurrence of a bridge phenomenon in which a bridge is formed across Al metallizations, spaced away from one another on the same level surface, or a notch phenomenon in which the width of the metallization is partially narrowed.
Accordingly, in order to reduce the reflectance of the Al metallization, there is formed on antireflective film, composed of e.g. TiN, TiW, WSi and W or Ti, on the Al metallization.
Accordingly, a triple-level metallization structure has been proposed recently as a multilevel metallization structure. However, if such triple-level metallization structure is employed by the multilevel metallization structure, there is a problem with the metallization interconnection resistance at an opening hole where upper and lower metallizations are connected to each other. This problem adversely influences the operation speed of the integrated circuit. There is another problem in the conventional multilevel metallization structure that the upper metallization is liable to peel off at the portion where the upper and lower metallizations are connected to each other.